In communications, a transmitter uses a particular modulation format to map bits of data to symbols, which it then transmits as a signal over a communications channel to a receiver. The receiver applies an inverse process of demodulation to the received signal to produce estimates of the symbols, the data bits, or both. During its transmission over the channel, the signal may experience noise and/or distortion. Noise and/or distortion may also be contributed to the signal by components of the transmitter and/or receiver. The noise and/or distortion experienced by the signal may lead to errors in the symbols or bits recovered at the receiver.
The reliability of a communications channel may be characterised by the Bit Error Ratio or Bit Error Rate (BER), which measures the ratio of the expected number of erroneously received bits (or symbols) to the total number of bits (or symbols) that are transmitted over the communications channel. A given application may have a maximum BER tolerance. For example, an application may require that the BER not exceed 10−16.
Forward Error Correction (FEC) techniques may be used to reduce the BER. FEC encoding performed at a transmitter maps input information bits to FEC-encoded bits, which include redundant information, such as parity or check symbols. When a systematic FEC code is employed, the FEC-encoded bits output from the FEC encoder consist of redundant bits and the information bits that were input to the FEC encoder. FEC decoding subsequently performed at a receiver uses the redundant information to detect and correct bit errors. In an optical communication network using FEC, the bits of data that undergo modulation at the transmitter have already been FEC-encoded. Similarly, the demodulation performed at the receiver is followed by FEC decoding.
FEC is advantageous in that it may permit error control without the need to resend data packets. However, this is at the cost of increased overhead. The amount of overhead or redundancy added by a FEC encoder may be characterized by the information rate R, where R is defined as the ratio of the amount of input information to the amount of data that is output after FEC encoding (which includes the overhead). For example, if FEC encoding adds 25% overhead, then for every four information bits that are to be FEC-encoded, the FEC encoding will add 1 bit of overhead, resulting in 5 FEC-encoded data bits to be transmitted to the receiver. This corresponds to an information rate R=4/5=0.8.
A variety of techniques for FEC encoding and decoding are known. The combination of a FEC encoding technique and the corresponding FEC decoding technique are herein referred to as a “FEC scheme.” Stronger FEC schemes provide better protection (i.e., better error detection and correction) by adding more redundancy. However, this is at the expense of a lower information rate. Circuitry to implement stronger FEC schemes may also take up more space, may be more costly, and may produce more heat than circuitry to implement weaker (i.e., higher-rate) FEC schemes.
A FEC scheme may be implemented using hard decision FEC decoding or soft decision FEC decoding. In hard decision FEC decoding, using BPSK as an illustrative example, a firm decoding decision is made by comparing a received signal to a threshold; anything above the threshold is decoded as “1” and anything below the threshold is decoded as “0”. In soft decision FEC decoding, additional probability bits are used to provide a more granular indication of the received signal; in addition to determining whether the incoming signal is “1” or “0” based on the threshold, the soft decision FEC decoding also provides an indication of confidence in the decision. While soft decision FEC decoding is more robust than hard decision FEC decoding, it is also more complicated to implement.
A FEC scheme may be selected to satisfy a desired BER tolerance. For example, a hard decision FEC scheme may take input bits having a maximum BER of 10−4, (i.e., 1 bit error for each 10000-bit block), and may produce output bits having a maximum BER of 10−16 (10−12 bit errors for each 10000-bit block). It is of interest to maximize the information rate, while satisfying a desired BER tolerance.
U.S. Pat. No. 9,537,608 describes a FEC technique referred to as staggered parity, in which parity vectors are computed such that each parity vector spans a set of frames; a subset of bits of each frame is associated with parity bits in each parity vector; and a location of parity bits associated with one frame in one parity vector is different from that of parity bits associated with the frame in another parity vector.